Energy Efficient STT-MRAM Writing Circuits
The Problem
STT-MRAM is a leading candidate to replace SRAM and DRAM in traditional computing architectures due to its non-volatility, high scalability, and long retention time. In addition to these benefits, MRAM cells may also withstand high radiation and high temperatures, making them attractive for many industrial applications. However, a lingering impediment to wide-spread adoption of MRAM is the excessive energy it takes to write data to Magnetic Tunnel Junctions (MTJs) though the pinned ferromagnetic layer.
The Solution
Researchers at the University of Tennessee have developed a novel method of writing to MTJs which reduces write power by up to 75%, without additional area penalty. The designs use alternatives to CMOS logic for certain tasks, and are thus able to relocate the DC power supplies and minimize quiescent current. The researchers have implemented several variants of these circuits which are compatible with traditional CMOS technology.
Pictured above: block diagram for one of several proposed MTJ Write Circuits
Benefits
| Benefit |
|---|
| Write energy reduced up to 75% |
| Tested with 45nm CMOS technology at 50MHz clock frequency |
| No additional transistor count over state of the art STT-MRAM write circuitry |
| Ideal for low power, high efficiency applications like IoT and embedded systems |
More Information
- Gregory Sechrist, JD
- Associate Technology Manager, Multi Campus Office
- 865-974-1882 | gsechris@tennessee.edu
- UTRF Reference ID: 22158
- Patent Status: Patent Pending
Innovators
Dr. Himanshu Thapliyal
Professor, Electrical Engineering & Computer Science, Tickle College of Engineering, University of Tennessee Knoxville
Dr. Thapliyal received his PhD in 2011 from the University of South Florida, Tampa, where he received the "Distinguished Graduate Achievement Award." From 2012-2014, he worked as a designer of processor test solutions at Qualcomm. He joined as an Assistant Professor at the University of Kentucky, Lexington in 2014 and served as an Associate Professor until he joined the University of Tennessee in 2022. He has been ranked in the top 50 scientists throughout the world in computer hardware and architecture, and is the recipient of both the 2019 NSF CAREER award and the 2020 IEE-CS TCVLSI Mid-Career Research Achievement Award. He has authored over 150 journal/conference articles with over 4,800 citations, and holds 3 U.S. Patents for his inventions.
Read more about Dr. Himanshu Thapliyal